Timing Diagrams: Formalization and Algorithmic Verification

Timing diagrams are popular in hardware design. They have been formalized for use in reasoning tasks, such as computer-aided veriication. These eeorts have largely treated timing diagrams as interfaces to established notations for which veriication is decidable; this has restricted timing diagrams to expressing only regular language properties. This paper presents a timing diagram logic capable of expressing certain context-free and context-sensitive properties. It shows that veriication is decidable for properties expressible in this logic. More speciically, it shows that containment of !-regular languages generated by B uchi automata in timing diagram languages is decidable. The result relies on a correlation between timing diagram and reversal bounded counter machine languages.